The present invention concerns a device comprising a processor designed in particular for processing the Viterbi algorithm.
The Viterbi algorithm is a known digital signal processing technique used in various fields in which it is necessary to estimate the value of the bits of a digital bit stream. These fields include convolutional decoding and equalization in digital demodulation.
The algorithm may be implemented by means of a generalized digital signal processor. This type processor is not specifically designed for processing this algorithm and to do so requires a very large number of instructions. The processing time, being dependent on the number of instructions to execute, is therefore long.
It is routine for additional processing to be needed in a signal processing circuit.
A first solution is to provide the signal processor with sufficient power to process the Viterbi algorithm and for such additional processing. Assuming that a processor with sufficient power were available, it would necessarily be relatively costly.
A second solution is to assign the processing of the Viterbi algorithm to a component designed specifically for this purpose, for example the FUJITSU MB 86620 Viterbi processor. In this case the signal processing circuit requires at least two components and it is therefore larger and more costly. Also, it does not lend itself well to miniaturization which is indispensible in some applications.
An object of the present invention is therefore a device designed in particular to process the Viterbi algorithm which does not use any dedicated component but a generalized signal processor for which the power needed for such processing has been reduced. This device is also designed to be integrated into a single component.